`timescale 1ns / 1ps 
module tb();
    reg rst, clk;    
    wire [15:0] sop, eop, vld;
    wire [31:0] data_out [0:15]; 
    reg [15:0] data_in_vld;
    reg [31:0] data_in_data [0:15];
    integer i;


    initial begin            
        $dumpfile("tb.vcd");        
        $dumpvars(0, tb);    
    end

    initial begin
        rst = 1;
        clk = 1;
        forever begin
            #10 clk = ~clk;
        end
    end


    initial begin
        #30
        rst <= 0;

        for (i=0; i<16; i=i+1) begin
            data_in_vld[i] <= 1;
            data_in_data[i] <= 1282;
        end
    end

    initial
        #20000000 $finish;

    top m(.clk(clk), .rst(rst),
        .data_in_data(data_in_data), .data_in_vld(data_in_vld), 
        .sop(sop), .eop(eop), .vld(vld), .port_data_out(data_out));
endmodule